1. Field of the Invention
The present invention relates to an image processing apparatus using a logic circuit, which can be reconfigured in operation, and a method for controlling the same.
2. Description of the Related Art
An FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device) have been conventionally known as logic circuits having logical configurations, which can be reconfigured during circuit operation. Also, in recent years, a reconfigurable processor having a logical configuration, which can be more dynamically reconfigured during system operation, is coming into practical use.
Of conventional techniques that use reconfigurable logic circuits as described above, especially those that use reconfigurable processors, have often been proposed. Japanese Patent Laid-Open No. 2006-285792, for example, proposes an apparatus including a processing unit that can perform a plurality of types of image processing, and a control unit that controls the processing unit in accordance with attribute information indicating the contents of image processing for respective pixels, which form the input image. This makes it possible to perform desired image processing while avoiding increases in, for example, the circuit scale and the power consumption using not all types of hardware dedicated to respective types of image processing, each according to attribute information corresponding to a pixel of interest.
Also, Japanese Patent Laid-Open No. 2006-065786 proposes an apparatus including a reconfigurable circuit that has a plurality of logical configurations with variable functions, and a setting unit that sets the functions of the logical configurations. Note that the setting unit reduces the power consumed by a function switching process, by setting the functions of at least some of the plurality of logical configurations to the same function with a high frequency of appearance for a predetermined period.
However, the conventional techniques pose the following problems. A reconfigurable processor has a plurality of circuit configuration planes formed from multifunction elements, which are called PEs (Processor Elements) and have a primitive operation function. The circuit-configuration information (configuration data) of the reconfigurable processor is formed using a PE as a basic unit. For this reason, the reconfigurable processor has configuration data in an amount smaller than those of an FPGA and CPLD formed for each logic gate, and therefore has a circuit that can be reconfigured within a time shorter than those in an FPGA and CPLD.
Nevertheless, it takes a predetermined time to change the circuit configuration of the reconfigurable processor because this change takes place through a plurality of procedures, such as switching trigger detection for the circuit configuration, a circuit operation stop, configuration switching, and a circuit operation restart. Therefore, when image processing is performed for image data to be processed while switching the processing circuit in accordance with the pieces of attribute information of pixels that form the image data, as in the technique described in Japanese Patent Laid-Open No. 2006-285792, the number of times of switching of the configuration data increases as the attribute information is frequently switched. As a result, the temporal overhead incurred in switching the configuration data increases, leading to a lengthy processing time.
Japanese Patent Laid-Open No. 2006-065786 proposes a method for reducing a temporal overhead incurred in frequently switching the configuration data, as described above. The temporal overhead required to switch the configuration data to the one according to a corresponding attribute can be effectively reduced by fixing a processing-circuit function corresponding to a specific attribute with a high frequency of appearance in processed image data to one of the plurality of circuit configuration planes, as described in Japanese Patent Laid-Open No. 2006-065786.
Nevertheless, when image processing is performed for image data by scanning it in a predetermined sequence as in image processing of, for example, a printer, the number of times of switching of the configuration data differs depending on the distribution of attribute information in the scanning direction even when certain pieces of attribute information of pixels that form the image data have the same frequency. The amount of configuration data differs depending on the circuit function and circuit scale to be realized, so the time taken for configuration switching, in turn, changes. In other words, if a given attribute continuously appears in the scanning direction although its frequency of appearance is high, both the number of times of configuration switching and the total time taken for switching may decrease. In contrast, if a given attribute intermittently appears in the scanning direction although its frequency of appearance is low, both the number of times of configuration switching and the total time taken for switching may increase. Furthermore, even if given attributes have the same frequency of appearance, the total time taken for configuration switching may differ if the processing contents differ. That is, it is difficult to optimally fix a processing-circuit function corresponding to an attribute with a high frequency of appearance in processed image data based only on the frequency of appearance of each attribute.